1. Field of the Invention
The present invention relates to a technology for designing a large-scale semiconductor integrated circuit, or particularly to a method of analyzing a source current across a logic circuit in a large-scale semiconductor integrated circuit and a technology for circuit designing with the method.
2. Description of the Related Art
As electronic devices in a large-scale integrated circuit (referred to as “LSI”, hereinafter) have been reduced in the size, digital circuits patterned in the LSI are scaled out and improved in an operation speed. However, such LSIs and their application systems generally suffer from degradation in the performance due to the generation of noises which results from a change in the source current flowing across the LSI circuits during the operation.
FIG. 10 illustrates a mixed analog/digital integrated circuit (referred to as AD mixed LSI hereinafter). As shown, a single semiconductor chip mounts an analog-to-digital converter (ADC) for converting analog signals received from an outside to a digital signal at high accuracy, analog circuits including a clock generator circuit (PLL) for supplying a high-speed clock signal to built-in digital circuits, and the digital circuits including a microprocessor (CPU), and a digital signal processor (DSP) for processing the input signals.
In such an AD hybrid LSI chip, substrate noises generated from the digital circuits may leak and dissipate via the silicon substrate, the LSI chip package, or the wirings on a printed circuit board (PCB) to the analog circuits of which operations are thus disturbed. More particularly, the ADC may be declined in the accuracy of conversion, the PLL may be increased in the fracture of clock frequency, and the performance of the chip itself may thus be degraded or operate in error.
The principal cause of substrate noise generation is a change in voltage generated when the source current of the digital circuits flowing through internal power-supply and ground wirings, which connect the external power supply to the LSI chip, interacts with the parasitic impedances parasitic on those wirings on the basis of physical laws such as Ri and Ldi/dt.
Electromagnetic noises emitted from the LSI may also interfere and decline the operation of the peripheral electronic circuits. The electromagnetic noises is caused by the electromagnetic interaction which reflects a change in the source current of the digital circuits.
As clearly understood, the generation of noises largely depends on a change in the source current. It is hence desired to provide an analysis method for estimating waveform of the source current in each large-scale digital circuit block at high speed and high accuracy, by which VLSI designers can apply effectively measures to avoid.
A couple of conventional methods of analyzing the waveform of a source current are referenced. A first method includes expanding the digital circuits to a transistor level and using a circuit simulator for transition analysis thus to examine the waveform of the source current. A second method includes approximating the waveform of a consumed current at each logic gate in the digital circuits to a triangle wave. The triangle wave represents that the charging and discharging processes of load impedance in the switching operation of the logic gate complete within switching time. Then, the waveforms of the currents of the digital circuits are summed to have a waveform of the source current (K. Shimazaki, H. Tsujikawa, S. Kojima, and S. Hirano, “LEMINGS: LSI's EMI-Noise Analysis with Gate Level Simulator”, the proceedings of IEEE, ISQED2000).
The two conventional methods have the following drawbacks. The first method provides a higher level of the analysis accuracy but increases the execution time required for the circuit simulation on a large-scale digital circuit and will hence be unsuited for particular applications, such as design optimization of the source/grounding system for minimizing the generation of noises, where the simulation has to be repeated at each requirement of the design. High-speed simulation is expected by the use of logic simulators in the second method. However, in practice, the digital circuit permits the charging and discharging electricity to be moved at a high speed due to the re-distribution of charges among the parasitic capacitor at the initial state of the switching operation. This is followed by the external source supplying a charge which has a time constant a few times greater than the switching period. The second method fails to include those steps. Accordingly, the waveform of the source current will hardly be reproduced at high accuracy. The second method will be unsuited for analyzing noises sensitive to a change with time in the source current.